1. Field of the Invention
This invention relates to computer systems and more particularly to an improved system and method for testing and debugging a multiprocessing interrupt controller by using a single processor for simulating a multiprocessing environment.
2. Description of the Relevant Art
Computer systems employing multiple processing units hold a promise of economically accommodating performance capabilities that surpass those of current single-processor based systems. Within a multiprocessing environment, rather than concentrating all the processing for an application in a single processor, tasks are divided into groups or "threads" that can be handled by separate processors. The overall processing load is thereby distributed among several processors, and the distributed tasks may be executed simultaneously in parallel. The operating system software divides various portions of the program code into the separately executable threads, and typically assigns a priority level to each thread.
FIG. 1 is a block diagram of a so-called symmetrical multiprocessing system 10 including a plurality of processing units 12A-12C. Each processing unit 12A-12C includes a processing core 14A-14C, a cache memory 16A-16C, and a bus interface 18A-18C, respectively. The processing units 12A-12C are coupled to a main memory 20 via a system bus 22. A pair of I/O devices 24 and 26 are further coupled to system bus 22.
The multiprocessing system 10 of FIG. 1 is symmetrical in the sense that all processing units 12A-12C share the same memory space (i.e., main memory 20) and access the memory space using the same address mapping. The multiprocessing system 10 is further symmetrical in the sense that all processing units 12A-12C share equal access to the same I/O subsystem.
In general, a single copy of the operating system software as well as a single copy of each user application file is stored within main memory 20. Each processing unit 12A-12C executes from these single copies of the operating system and user application files. Although processing cores 14A-14C may be executing code simultaneously, it is noted that only one of the processing units 12A-12C may assume mastership of the system bus 22 at a given time. Thus, a bus arbitration mechanism (not shown) is provided to arbitrate concurrent bus requests of two or more processing units and to grant mastership to one of the processing units based on a predetermined arbitration algorithm. A variety of bus arbitration techniques are well-known.
An important consideration with respect to symmetrical multiprocessing systems is the handling and distribution of interrupts generated by various system resources. For example, in the system of FIG. 1, I/O devices 24 and 26 may each assert a respective interrupt signal based on the occurrence (or non-occurrence) of a particular event. As will be appreciated by those of skill in the art, interrupts are routinely generated by system resources such as keyboard devices, printers, and timers, among other things. Many systems also accommodate software interrupts whereby an interrupt may be asserted in response to software command. Due to the number of different interrupts that may occur within a system, it is desirable to provide a mechanism to efficiently manage and distribute the interrupts to achieve optimal system performance and bus utilization.
One technique for handling interrupts employs a centralized interrupt controller that is capable of receiving a plurality of interrupts and of prioritizing and distributing the interrupts amongst the various processing units. As can readily be appreciated, a properly functioning multiprocessing interrupt controller is required to process a complex array of signals and interface with a large number of logical units. Accordingly, the testing and debugging of a multiprocessing interrupt controller is generally complex and difficult. Typically, an external stimulus is provided from an external source into the multiprocessing interrupt controller, which requires a complex test apparatus. To verify the correctness of the result, a multiprocessing environment is generally employed. Thus, each of the processing units within the test environment must run independently and verify the correctness of the provided stimulus. Accordingly, there is a need for a more efficient and reliable method of testing a multiprocessing interrupt controller.